Publications

Found 3 results
Filters: Author is Chih-Wei Chang and Keyword is logic synthesis  [Clear All Filters]
2004
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
2001
C. - W. Chang, Hu, B., and Marek-Sadowska, M., “In-place delay constrained power optimization using functional symmetries”, in Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings, 2001, pp. 377 -382.
C. - W. Chang and Marek-Sadowska, M., “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.