Single-pass redundancy-addition-and-removal

TitleSingle-pass redundancy-addition-and-removal
Publication TypeConference Paper
Year of Publication2001
AuthorsChang, C-W, Marek-Sadowska, M
Conference NameComputer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Keywordscandidate wires, combinational circuits, combinational logic restructuring technique, incremental logic restructuring, logic CAD, logic gates, logic synthesis, logic testing, overall circuit functionality, reasoning scheme, redundancy, redundancy-addition-and-removal, rewiring technique, single-pass technique, speedup, target wire, timing, timing estimation, trial-and-error redundancy testing, wiring
AbstractRedundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire w a. Addition of wa makes wt redundant and hence removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, the search for valid alternative wires requires trial-and-error redundancy testing of a potentially large set of candidate Wires. We study the fundamental theory behind this technique and propose a new reasoning scheme which directly identifies alternative wires without performing trial-and-error tests. Experimental results show up to 15 times speedup in comparison to the best techniques in literature