Publications

Found 5 results
Filters: Keyword is integrated logic circuits  [Clear All Filters]
2003
C. - K. Tsai and Marek-Sadowska, M., “Modeling crosstalk induced delay”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
1998
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
1996
A. Vittal, Ha, H., Brewer, F., and Marek-Sadowska, M., “Clock skew optimization for ground bounce control”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
1992
B. Chen and Marek-Sadowska, M., “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
1991
S. Lin and Marek-Sadowska, M., “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.