Timing driven placement of pads and latches

TitleTiming driven placement of pads and latches
Publication TypeConference Paper
Year of Publication1992
AuthorsChen, B, Marek-Sadowska, M
Conference NameASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International
Date Publishedsep
Keywordscircuit layout CAD, flip-flops, heuristic approach, I/O pads, integrated logic circuits, latches, logic CAD, path delay constraints, performance loss, sequential circuits, sequential elements, timing-driven placement, VLSI, VLSI circuit
AbstractA heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performance