Title | Timing driven placement of pads and latches |
Publication Type | Conference Paper |
Year of Publication | 1992 |
Authors | Chen, B, Marek-Sadowska, M |
Conference Name | ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International |
Date Published | sep |
Keywords | circuit layout CAD, flip-flops, heuristic approach, I/O pads, integrated logic circuits, latches, logic CAD, path delay constraints, performance loss, sequential circuits, sequential elements, timing-driven placement, VLSI, VLSI circuit |
Abstract | A heuristic approach to the placement of I/O pads and sequential elements prior to the layout of a VLSI circuit is presented. The input information for the algorithm is the structure of the circuit and its path delay constraints. Experimental results suggest that the loss in performance can be substantial (on the order of 10%) when pads and/or latches are placed without consideration of performance |
DOI | 10.1109/ASIC.1992.270313 |