A fast and efficient algorithm for determining fanout trees in large networks

TitleA fast and efficient algorithm for determining fanout trees in large networks
Publication TypeConference Paper
Year of Publication1991
AuthorsLin, S, Marek-Sadowska, M
Conference NameDesign Automation. EDAC., Proceedings of the European Conference on
Date Publishedfeb
Keywordsbuffer area minimisation, circuit layout CAD, delay analysis, fanout trees, heuristic algorithm, integrated logic circuits, large networks, logic CAD, optimal selection, optimisation, specified timing constraints, technology mapping, trees (mathematics), VLSI, VLSI circuit design
AbstractThe authors present a heuristic algorithm the optimal selection of the fanout tree structures in VLSI circuit design. The algorithm minimizes area of the added buffers under the specified timing constraints. The algorithms described in the literatures solve a simpler problem of minimizing the circuit's timing without taking into account the area increase introduced by the buffers. Experimental results demonstrate that the authors' approach is very fast and efficient, particularly for large examples whose solution spaces are very large
DOI10.1109/EDAC.1991.206466