Cost-free scan: a low-overhead scan path design

TitleCost-free scan: a low-overhead scan path design
Publication TypeJournal Article
Year of Publication1998
AuthorsLin, C-C, Marek-Sadowska, M, Lee, T-C, Chen, K-C
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination852 -861
Date Publishedsep
Keywordscircuit testability, controllability, cost-free scan, design for testability, DFT, flip-flops, free-scan flip-flops, integrated circuit testing, integrated logic circuits, logic design, logic testing, low-overhead scan path design, partial-scan designs, scan chain, scan overhead reduction, sequential circuits, test mode
AbstractConventional scan design imposes considerable area and delay overheads. To establish a scan chain in the test mode, multiplexers at the inputs of flip-flops and scan wires are added to the actual design. However, the functionality of the functional logic has not been utilized for the test purposes. We propose a low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the functional logic. We show how to analyze the circuit to determine all the free-scan flip-flops and select the best input vector to establish the maximum number of free-scan flip-flops for the scan chain design. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks. In full-scan designs, as many as 89% of the flip-flops are found free-scannable. In the partial-scan designs, we assume that selecting flip-flops for scan to break sequential cycles is used to increase circuit testability. Reduction can be as high as 97% in scan flip-flops needed to break sequential cycles