Publications

Found 6 results
Filters: Author is Chao-Yang Yeh  [Clear All Filters]
2007
C. - Y. Yeh and Merek-Sadowska, M., “Timing-Aware Power-Noise Reduction in Placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 527 -541, 2007.
2005
C. - Y. Yeh and Marek-Sadowska, M., “Skew-programmable clock design for FPGA and skew-aware placement”, in FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005, pp. 33–40.
C. - Y. Yeh and Marek-Sadowska, M., “Timing-aware power noise reduction in layout”, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 627 - 634.
2004
C. - Y. Yeh and Marek-Sadowska, M., “Sequential delay budgeting with interconnect prediction”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
2003
C. - Y. Yeh and Marek-Sadowska, M., “Delay budgeting in sequential circuit with application on FPGA placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
C. - Y. Yeh and Marek-Sadowska, M., “Minimum-area sequential budgeting for FPGA”, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.