| Title | Timing-aware power noise reduction in layout |
| Publication Type | Conference Paper |
| Year of Publication | 2005 |
| Authors | Yeh, C-Y, Marek-Sadowska, M |
| Conference Name | Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on |
| Date Published | nov. |
| Keywords | cell power noise estimation, circuit layout, circuit optimisation, decap padding, gate sizing, integrated circuit layout, integrated circuit noise, linear program sequence, linear programming, power grid analysis, switching frequency, timing constraint, timing-aware power noise reduction |
| Abstract | In this paper, we propose a timing-aware power-noise reduction technique. Our approach consists of prediction and correction steps. Before placement, we estimate the power noise of each cell considering switching frequency of cells which, after placement, will most likely be in the neighborhood. If a frequently switching cell has neighbors which switch infrequently, it is unlikely that this cell will suffer from a power noise problem. Based on the cell power noise estimation, we add decap padding to each cell. Then we invoke a standard cell placement tool and perform power grid analysis. We eliminate the power grid noise by gate sizing. Our technique can reallocate decaps to improve power noise, power consumption, and timing. The gate sizing is based on the sequence of linear programs (SLP) formulation, and it can be solved efficiently. Experimental results show that our techniques can effectively reduce power noise and meet timing constraints. |
| DOI | 10.1109/ICCAD.2005.1560143 |
