Publications
Found 5 results
Filters: Keyword is logic testing and Author is Chih-Chang Lin [Clear All Filters]
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
, “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
, “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
, “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
