Test point insertion: scan paths through combinational logic

TitleTest point insertion: scan paths through combinational logic
Publication TypeConference Paper
Year of Publication1996
AuthorsLin, C-C, Marek-Sadowska, M, Cheng, K-T, Lee, T-C
Conference NameDesign Automation Conference Proceedings 1996, 33rd
Date Publishedjun,
Keywordscircuit CAD, combinational circuits, combinational logic, design for testability, design-for-testability, functional logic, integrated circuit design, logic CAD, logic testing, low-overhead scan design methodology, scan paths, test point insertion, timing-driven partial scan design
AbstractWe propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability (DFT) overhead on area or timing can be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead for the full scan design. We also discuss its application to timing-driven partial scan design