| Title | Test point insertion: scan paths through combinational logic |
| Publication Type | Conference Paper |
| Year of Publication | 1996 |
| Authors | Lin, C-C, Marek-Sadowska, M, Cheng, K-T, Lee, T-C |
| Conference Name | Design Automation Conference Proceedings 1996, 33rd |
| Date Published | jun, |
| Keywords | circuit CAD, combinational circuits, combinational logic, design for testability, design-for-testability, functional logic, integrated circuit design, logic CAD, logic testing, low-overhead scan design methodology, scan paths, test point insertion, timing-driven partial scan design |
| Abstract | We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability (DFT) overhead on area or timing can be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead for the full scan design. We also discuss its application to timing-driven partial scan design |
| DOI | 10.1109/DAC.1996.545585 |
