Scan paths through functional logic

TitleScan paths through functional logic
Publication TypeConference Paper
Year of Publication1996
AuthorsLin, C-C, Marek-Sadowska, M, Cheng, K-T, Lee, T-C
Conference NameCustom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996
Date Publishedmay
Keywordsarea overhead, ATPG, automatic testing, boundary scan testing, combinational logic, delay overhead, delays, design for testability, DFT overhead, flip-flops, functional logic, input vectors, integrated circuit testing, logic testing, low-overhead scan design methodology, scan paths, sequential circuits, test-mode point insertion technique
AbstractConventional scan design imposes considerable area and delay overhead due to the use of larger flip-flops and additional connections between flip-flops. We propose a low-overhead scan design methodology which exploits the possibility of utilizing input vectors and the test-mode point insertion technique to establish scan paths through the combinational logic. The technique re-uses the existing functional logic; as a result, the DFT overhead can be reduced