Title | Scan paths through functional logic |
Publication Type | Conference Paper |
Year of Publication | 1996 |
Authors | Lin, C-C, Marek-Sadowska, M, Cheng, K-T, Lee, T-C |
Conference Name | Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996 |
Date Published | may |
Keywords | area overhead, ATPG, automatic testing, boundary scan testing, combinational logic, delay overhead, delays, design for testability, DFT overhead, flip-flops, functional logic, input vectors, integrated circuit testing, logic testing, low-overhead scan design methodology, scan paths, sequential circuits, test-mode point insertion technique |
Abstract | Conventional scan design imposes considerable area and delay overhead due to the use of larger flip-flops and additional connections between flip-flops. We propose a low-overhead scan design methodology which exploits the possibility of utilizing input vectors and the test-mode point insertion technique to establish scan paths through the combinational logic. The technique re-uses the existing functional logic; as a result, the DFT overhead can be reduced |
DOI | 10.1109/CICC.1996.510603 |