Publications
, “Speeding up power estimation by topological analysis”, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
, “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
, “Technology mapping and circuit depth optimization for field programmable gate arrays”, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
, “Verifying equivalence of functions with unknown input correspondence”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
, “Technology mapping via transformations of function graphs”, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
, “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
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