Speeding up power estimation by topological analysis

TitleSpeeding up power estimation by topological analysis
Publication TypeConference Paper
Year of Publication1995
AuthorsCheng, DI, Marek-Sadowska, M, Cheng, K-T
Conference NameCustom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995
Date Publishedmay
KeywordsBDD-based techniques, CMOS logic circuits, combinational circuits, estimation theory, network topology, optimal algorithm, power estimation, probability, process speedup, supergate structures, switching theory, topological analysis
AbstractWe present an efficient technique to speedup the power estimation process for combinational circuits. Our approach is based on a topological analysis of the underlying circuit using the concept of supergates. We also present an optimal algorithm for calculating the supergate structures. In addition to speeding up, we also point out that certain nodes in a given circuit are more crucial than other nodes to be estimated accurately. Experimental results are very encouraging