| Title | Technology mapping and circuit depth optimization for field programmable gate arrays |
| Publication Type | Conference Paper |
| Year of Publication | 1993 |
| Authors | Chang, S-C, Marek-Sadowska, M |
| Conference Name | Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993 |
| Date Published | may |
| Keywords | ASIC, Boolean network, circuit depth optimization, field programmable gate arrays, lookup-table-type, partitioning approach, rule-based postprocessor, total number minimisation, two-step technology mapping algorithm |
| Abstract | A two-step technology mapping algorithm for lookup-table-type FPGAs (field programmable gate arrays) is proposed. In the first step, the technology mapper attempts to minimize the total number of TLUs (table look-ups) used and the same time to keep the length of the critical path short. Then, it is followed by a rule-based postprocessor which maximally decreases the depth of a circuit. The good results obtained are attributed to the fact that the partitioning approach employed is tightly coupled with the size of the target TLU blocks |
| DOI | 10.1109/CICC.1993.590373 |
