Technology mapping and circuit depth optimization for field programmable gate arrays

TitleTechnology mapping and circuit depth optimization for field programmable gate arrays
Publication TypeConference Paper
Year of Publication1993
AuthorsChang, S-C, Marek-Sadowska, M
Conference NameCustom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Date Publishedmay
KeywordsASIC, Boolean network, circuit depth optimization, field programmable gate arrays, lookup-table-type, partitioning approach, rule-based postprocessor, total number minimisation, two-step technology mapping algorithm
AbstractA two-step technology mapping algorithm for lookup-table-type FPGAs (field programmable gate arrays) is proposed. In the first step, the technology mapper attempts to minimize the total number of TLUs (table look-ups) used and the same time to keep the length of the critical path short. Then, it is followed by a rule-based postprocessor which maximally decreases the depth of a circuit. The good results obtained are attributed to the fact that the partitioning approach employed is tightly coupled with the size of the target TLU blocks
DOI10.1109/CICC.1993.590373