Publications

Found 5 results
Filters: Keyword is timing circuits  [Clear All Filters]
2009
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
2007
C. - Y. Yeh and Merek-Sadowska, M., “Timing-Aware Power-Noise Reduction in Placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 527 -541, 2007.
2004
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
C. - Y. Yeh and Marek-Sadowska, M., “Sequential delay budgeting with interconnect prediction”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
2003
A. Mukherjee and Marek-Sadowska, M., “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.