Clock and power gating with timing closure

TitleClock and power gating with timing closure
Publication TypeJournal Article
Year of Publication2003
AuthorsMukherjee, A, Marek-Sadowska, M
JournalDesign Test of Computers, IEEE
Pagination32 - 39
Date Publishedmay-june
Keywordsclock gating, deep-submicron circuits, delay, delays, dynamic power dissipation, integrated circuit design, local power supply voltage, low-power electronics, power gating, power ground networks, power supply circuits, power supply variations, timing circuits, timing closure
AbstractAssuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.