Title | Clock and power gating with timing closure |
Publication Type | Journal Article |
Year of Publication | 2003 |
Authors | Mukherjee, A, Marek-Sadowska, M |
Journal | Design Test of Computers, IEEE |
Volume | 20 |
Pagination | 32 - 39 |
Date Published | may-june |
ISSN | 0740-7475 |
Keywords | clock gating, deep-submicron circuits, delay, delays, dynamic power dissipation, integrated circuit design, local power supply voltage, low-power electronics, power gating, power ground networks, power supply circuits, power supply variations, timing circuits, timing closure |
Abstract | Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation. |
DOI | 10.1109/MDT.2003.1198683 |