Timing-Aware Multiple-Delay-Fault Diagnosis

TitleTiming-Aware Multiple-Delay-Fault Diagnosis
Publication TypeJournal Article
Year of Publication2009
AuthorsMehta, V, Marek-Sadowska, M, Tsai, K-H, Rajski, J
JournalComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Pagination245 -258
Date Publishedfeb.
Keywordsautomatic test pattern generation, automatic-test-pattern-generated sets, delay circuits, delay-defect-size estimations, diagnostic resolution, failure logs, fault diagnosis, n-detection, slower-than-nominal clock frequencies, timing circuits, timing-aware multiple-delay-fault diagnosis
AbstractWith feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility of n-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared to n -detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations.