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Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Analysis and methodology for multiple-fault diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Multiple fault diagnosis using n-detection tests”, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.