| Title | Analysis and methodology for multiple-fault diagnosis |
| Publication Type | Journal Article |
| Year of Publication | 2006 |
| Authors | Wang, Z, Marek-Sadowska, M, Tsai, K-H, Rajski, J |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 25 |
| Pagination | 558 - 575 |
| Date Published | march |
| ISSN | 0278-0070 |
| Keywords | circuit complexity, circuit diagnosis, circuit testing, diagnostic test patterns, failing pattern analysis, failure analysis, fault multiplicity, fault simulation, high diagnostic resolution, linear time complexity, logic testing, multiple-fault diagnosis, single-fault-based diagnostic algorithm |
| Abstract | In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time. |
| DOI | 10.1109/TCAD.2005.854624 |
