Publications
Found 8 results
Filters: Keyword is circuit analysis computing and Author is Malgorzata Marek-Sadowska [Clear All Filters]
“An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
, “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
, “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
, “A new hybrid methodology for power estimation”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
, “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
, “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
, “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
, “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
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