Title | Stepwise equivalent conductance circuit simulation technique |

Publication Type | Journal Article |

Year of Publication | 1993 |

Authors | Lin, S, Kuh, ES, Marek-Sadowska, M |

Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |

Volume | 12 |

Pagination | 672 -683 |

Date Published | may |

ISSN | 0278-0070 |

Keywords | circuit analysis computing, conductance circuit simulation technique, convergent, digital integrated circuits, digital MOS circuits, equivalent circuits, integration, linear equations, local truncation error, nonlinear resistive device, piecewise-linear functions, stepwise equivalent conductance model, SWEC |

Abstract | A circuit simulation technique based on a stepwise equivalent conductance model of a nonlinear resistive device is introduced. The major advantage of this technique is that it eliminates the need to employ Newton-Raphson iterations for the implicit integration. The technique, when applicable, is consistent, absolutely stable, and convergent. It is demonstrated that a second order of accuracy (the local truncation error for integration is of the cubic order of the time step used) is achieved by solving linear equations for each integration step. When applied to digital MOS circuits, the technique takes advantage of the fact that voltage waveforms can be modeled to a good approximation as piecewise-linear functions and thus provides further speedup in the simulation. The program, called SWEC, has been implemented, and has proved to be accurate and efficient on a large number of circuit examples. The results are compared with those for Relax2.3.iSPLICE3.0 XPsim. and SPECS2 |

DOI | 10.1109/43.277612 |