| Title | Rapid layout pattern classification |
| Publication Type | Conference Paper |
| Year of Publication | 2011 |
| Authors | Wuu, J-Y, Pikus, FG, Torres, A, Marek-Sadowska, M |
| Conference Name | Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific |
| Date Published | jan. |
| Keywords | CD threshold, circuit analysis computing, fast physical verification tool, industrial designs, integrated circuit layout, layout object printability, pattern classification, pattern matching, pattern matching-based tools, rapid layout pattern classification, runtime enhancement techniques, size 32 nm, size 45 nm, support vector machines, two-level hotspot pattern classification methodology |
| Abstract | Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs. |
| DOI | 10.1109/ASPDAC.2011.5722295 |
