| Title | A hybrid methodology for switching activities estimation |
| Publication Type | Journal Article |
| Year of Publication | 1998 |
| Authors | Cheng, DI, Cheng, K-T, Wang, DC, Marek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 17 |
| Pagination | 357 -366 |
| Date Published | apr |
| ISSN | 0278-0070 |
| Keywords | BDD, binary decision diagrams, Boolean functions, circuit analysis computing, CMOS circuits, CMOS logic circuits, delays, hybrid methodology, internal nodes, logic circuits, probabilistic model, probability, probability-based technique, sequential circuits, simulation-based technique, switching, switching activities estimation, user-specified control sequence, VLSI |
| Abstract | In this paper, we propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits. The new approach combines the advantages of the simulation-based techniques and the probability-based techniques. We use the user-specified control sequence for simulation, and treat the weakly correlated data inputs using the probabilistic model. The new approach, on one hand, is more accurate than the probabilistic approaches because the strong temporal and spatial correlations among control inputs are well taken into consideration. On the other hand, the new approach is much more efficient than the simulation-based approaches because the weakly correlated data inputs are not explicitly simulated. We also discuss the situation where BDD's are built in terms of internal nodes so that large circuits can he handled. Extensive experimental results are presented to show the effectiveness and efficiency of our algorithms |
| DOI | 10.1109/43.703825 |
