Publications

Found 5 results
Filters: Keyword is timing and Author is Chih-Wei Chang  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
A
C. - W. Chang and Marek-Sadowska, M., “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
E
T. Xiao, Chang, C. - W., and Marek-Sadowska, M., “Efficient static timing analysis in presence of crosstalk”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 335 -339.
F
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
N
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
S
C. - W. Chang and Marek-Sadowska, M., “Single-pass redundancy-addition-and-removal”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.