ATPG-based logic synthesis: an overview

TitleATPG-based logic synthesis: an overview
Publication TypeConference Paper
Year of Publication2002
AuthorsChang, C-W, Marek-Sadowska, M
Conference NameComputer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
Date Publishednov.
Keywordsadd-a-wire-and-remove-a-wire operation, ATPG-based logic synthesis, automatic test pattern generation, Boolean networks, circuit optimisation, complex logic transformations, gate-level Boolean networks, IC design, integrated circuit design, literal minimization, logic CAD, physical synthesis, power optimization, redundancy, redundancy-addition-and-removal, timing, timing optimization
AbstractThe ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is expressed using "don't cares" and we seek the best implementation that does not violate them. However, the calculation and storing of don't care information is CPU and memory-intensive. In this paper, we give an overview of logic synthesis approaches based on techniques developed for Automatic Test Pattern Generation (ATPG). Instead of calculating and storing don't cares explicitly, ATPG-based logic synthesis techniques calculate the flexibility implicitly. Low CPU and memory usage make those techniques applicable for practical industrial circuits. Also, the basic ATPG-based logic level operations create predictable, small layout perturbations, making an ideal foundation for efficient physical synthesis. Theoretical results show that an efficient, yet simple add-a-wire-and-remove-a-wire operation covers all possible complex logic transformations.