Publications
Found 10 results
Filters: Keyword is flip-flops and Author is Malgorzata Marek-Sadowska [Clear All Filters]
“Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
, “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
, “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
, “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
, “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
, “A global routing technique for wave-steered design methodology”, in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 2001, pp. 430 -436.
, “Functional scan chain testing”, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
, “Designing a via-configurable regular fabric”, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.
, “Delay budgeting in sequential circuit with application on FPGA placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
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