| Title | An integrated design flow for a via-configurable gate array |
| Publication Type | Conference Paper |
| Year of Publication | 2004 |
| Authors | Ran, Y, Marek-Sadowska, M |
| Conference Name | Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on |
| Date Published | nov. |
| Keywords | fixed metal masks, flip-flops, FPGA-based design, integrated circuit design, integrated circuit interconnections, integrated design flow, logic design, M1-M2 via mask, prefabricated logic blocks, standard-cell based design, VCGA-based design, via-configurable functional cells, via-configurable gate array, via-decomposable flip-flop |
| Abstract | In This work we present a complete physical design flow for a via-configurable gate array (VCGA). The VCGA is an array of prefabricated logic blocks and fixed metal masks. The block consists of via-configurable functional cells and a via-decomposable flip-flop. An M1-M2 via mask is used to define the block's functionality. Interconnects are customized using via masks. We developed a physical design flow for VCGA, which integrates a set of effective techniques. Here, we highlight the packing, cell-binding, and detailed-routing problems. We use our design flow to compare the VCGA-based and standard-cell/FPGA-based designs. Experimental results show the efficiency of our flow. |
| DOI | 10.1109/ICCAD.2004.1382644 |
