# Publications

Found 10 results

“An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.

, “Aggresors alignment for worst-case coupling noise”, in ICCAD '00: Proceedings of the 2000 international conference on Computer-aided design, 2000, pp. 48–54.

, “Aggressor alignment for worst-case coupling noise”, in ISPD '00: Proceedings of the 2000 international symposium on Physical design, 2000, pp. 48–54.

, “Aggressor alignment for worst-case crosstalk noise”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, pp. 612 -621, 2001.

, “Analysis and methodology for multiple-fault diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.

, “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.

, “Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic”, in ICCAL '89: Proceedings of the 2nd International Conference on Computer Assisted Learning, 1989, pp. 359–378.

, “Analysis of process variation's effect on SRAM's read stability”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.

, “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.

, “Automatic Sizing of Power/Ground (P/G) Networks in VLSI”, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.

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