Publications

Found 231 results
Journal Article
C. - W. Chang and Marek-Sadowska, M., “Theory of wire addition and removal in combinational Boolean networks”, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
C. - Y. Yeh and Merek-Sadowska, M., “Timing-Aware Power-Noise Reduction in Placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 26, pp. 527 -541, 2007.
M. Marek-Sadowska, “An Unconstrained Topological Via Minimization Problem for Two-Layer Routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 184 - 190, 1984.
Y. Ran and Marek-Sadowska, M., “Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 998 -1009, 2006.
A. Mukherjee and Marek-Sadowska, M., “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.

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