Wave steering to integrate logic and physical syntheses

TitleWave steering to integrate logic and physical syntheses
Publication TypeJournal Article
Year of Publication2003
AuthorsMukherjee, A, Marek-Sadowska, M
JournalVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
Pagination105 -120
Date Publishedfeb.
KeywordsBDD-type structures, binary decision diagram, binary decision diagrams, circuit CAD, CMOS logic circuits, combinational circuits, computation-intensive combinational circuits, datapath combinational circuits, electrical constraints, fast turn-around times, high level synthesis, high performance arithmetic circuits, high-throughput circuit generation, logic CAD, logic representation, network routing, pass transistor logic, pipeline arithmetic, PTL mapping, static CMOS combinational circuits, timing, two-phase clocking scheme, unified logic/physical synthesis scheme, very fine granular pipelining, VLSI, wave steering technique
AbstractWave steering is a unified logic and physical synthesis scheme that algorithmically generates high-throughput circuits with fast turn-around times. Binary decision diagram (BDD)-type structures are altered to satisfy certain electrical constraints, embedded in silicon with pass transistor logic (PTL), and pipelined to very fine granularity using a novel two-phase clocking scheme. This direct PTL mapping of a logic representation provides good electrical estimations to a front-end tool like the logic synthesizer at an early phase of the design cycle. We apply our wave steering technique to high throughput computation-intensive datapath combinational circuits. We achieve an average speedup of 4.2 times compared to standard cell (SC) implementations of high performance arithmetic circuits at the cost of only about 76% average increase in area. The results look extremely encouraging; all the more so, considering that we also achieve an average reduction of 27% in latency and 15% in power compared to SC circuits.