Publications

Found 231 results
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
C
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., “Fast post-placement rewiring using easily detectable functional symmetries”, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
D. Chang and Marek-Sadowska, M., “Partitioning sequential circuits on dynamically reconfigurable FPGAs”, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.

Pages