Temporofunctional crosstalk noise analysis

TitleTemporofunctional crosstalk noise analysis
Publication TypeConference Paper
Year of Publication2003
AuthorsChai, D, Kondratyev, A, Ran, Y, Tseng, K, Watanabe, Y, Marek-Sadowska, M
Conference NameDesign Automation Conference, 2003. Proceedings
Date Publishedjune
KeywordsASIC design, Boolean algebra, Boolean satisfiability, circuit operation, computability, crosstalk, delay model, electric noise measurement, gate delay, integrated circuit design, integrated circuit noise, integrated circuit testing, noise fault, SAT logic, signal functionality, signal timing, signal transition correlation, temporofunctional crosstalk noise analysis, time interval, timed Boolean logic
AbstractNoise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal transitions in multiple nets by considering both timing and functionality of the signals, and uses it in an analysis procedure to eliminate noise faults that cannot actually happen when such correlations are considered. It uses four-variable Boolean logic to characterize signal transitions in a time interval, and formulates Boolean satisfiability between aggressors and a victim under the min-max delay model for gates. The technique has been successfully applied to commercial ASIC designs and has eliminated up to 35% of delay noise faults reported by a state-of-the-art noise analysis tool.