Layout-driven hot-carrier degradation minimization using logic restructuring techniques

TitleLayout-driven hot-carrier degradation minimization using logic restructuring techniques
Publication TypeConference Paper
Year of Publication2001
AuthorsChang, C-W, Wang, K, Marek-Sadowska, M
Conference NameDesign Automation Conference, 2001. Proceedings
Keywordscircuit layout CAD, circuit optimisation, design-for-reliability tools, dielectric breakdown, discrete gate resizing, electromigration, electrostatic discharge, failure analysis, failure mechanisms, hot carriers, hot-carrier effect, incremental logic restructuring, integrated circuit layout, integrated circuit reliability, layout-driven hot-carrier degradation, logic CAD, logic restructuring techniques, long-term reliability, performance optimization issues, physical layout, pin reordering, post-layout design, reliability problems, rewiring
AbstractThe rapid advances in semiconductor manufacturing technology have created tough reliability problems. Failure mechanisms such as hot-carrier effect, dielectric breakdown, electrostatic discharge and electromigration have posed tremendous threats to the long-term reliability of VLSI circuits. As a result, designers not only need analysis tools to locate the problem, but also design-for-reliability tools to correct it. However, these problems often surface when the physical layout is done and relatively few logic changes can be made. In this paper, we target the performance optimization issues in the context of hot-carrier induced degradation. A layout driven approach combining rewiring, discrete gate resizing, and pin reordering is proposed. Experimental results show that rewiring-based incremental logic restructuring is a very powerful technique in post-layout design for reliability.