- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publications
, “Can pin access limit the footprint scaling?”, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
, “Vertical Slit Field Effect Transistor in ultra-low power applications”, in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 384 -390.
, “A study on cell-level routing for VeSFET circuits”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.
