Publications

Found 43 results
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2000
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
1999
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
1997
C. - C. Tsai and Marek-Sadowska, M., “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., “Starbist Scan Autocorrelated Random Pattern Generation”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
1996
C. - C. Tsai and Marek-Sadowska, M., “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
C. - C. Tsai and Marek-Sadowska, M., “Logic synthesis for testability”, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
C. - C. Tsai and Marek-Sadowska, M., “Multilevel logic synthesis for arithmetic functions”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.
1994
C. - C. Tsai and Marek-Sadowska, M., “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., “On computational complexity of a detailed routing problem in two dimensional FPGAs”, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
C. - C. Tsai and Marek-Sadowska, M., “Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms”, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
C. - C. Tsai and Marek-Sadowska, M., “Minimisation of fixed-polarity AND/XOR canonical networks”, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
1993
C. - C. Tsai and Marek-Sadowska, M., “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
1984
T. T. - K. Tarng, Marek-Sadowska, M., and Kuh, E. S., “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
1983
M. Marek-Sadowska and Tarng, T. T. - K., “Single-Layer Routing for VLSI: Analysis and Algorithms”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.

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