Scan encoded test pattern generation for BIST

TitleScan encoded test pattern generation for BIST
Publication TypeConference Paper
Year of Publication1997
AuthorsTsai, K-H, Rajski, J, Marek-Sadowska, M
Conference NameTest Conference, 1997. Proceedings., International
Date Publishednov
Keywordsautomatic testing, boundary scan testing, built-in self test, fault coverage, fault diagnosis, hardware cost, integrated circuit testing, logic testing, random pattern resistant faults, scan encoded test pattern generation, scan order, scan synthesis, scan-based BIST scheme, test vectors
AbstractThis paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test vectors which serve as centers of clusters from which the other vectors are derived by complementing at random their coordinates. The proposed method successfully tests the random pattern resistant faults, which is the major problem of traditional LFSR-based BIST, with lower hardware cost and a more efficient algorithm than previous methods. Experimental results demonstrate that a very high fault coverage can be achieved with much smaller test set than other pseudorandom pattern generation methods published so far