- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publications
, “An Unconstrained Topological Via Minimization Problem for Two-Layer Routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 184 - 190, 1984.
, “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
