| Title | Functional scan chain testing |
| Publication Type | Conference Paper |
| Year of Publication | 1998 |
| Authors | Chang, D, Lee, T-C, Cheng, K-T, Marek-Sadowska, M |
| Conference Name | Design, Automation and Test in Europe, 1998., Proceedings |
| Date Published | feb |
| Keywords | ATPG, automatic testing, fault detection, flip-flops, functional logic, functional scan chain testing, functional scan paths, logic testing, sequential circuits, sequential fault simulation, test point insertion |
| Abstract | Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (TPI) has been shown to be an effective technique to reduce the scan overhead. However, once the scan chain is allowed to go through functional logic, the traditional alternating test sequence is no longer enough to ensure the correctness of the scan chain. We identify the faults that affect the functional scan chain, and show a methodology to find tests for these faults. Our results have the number of undetected faults at only 0.006% of the total number of faults, or 0.022% of the faults affecting the scan chain |
| DOI | 10.1109/DATE.1998.655868 |
