- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Post-layout Logic Restructuring For Performance Optimization
| Title | Post-layout Logic Restructuring For Performance Optimization |
| Publication Type | Conference Paper |
| Year of Publication | 1997 |
| Authors | Jiang, Y-M, Krstic, A, Cheng, K-T, Marek-Sadowska, M |
| Conference Name | Design Automation Conference, 1997. Proceedings of the 34th |
| Date Published | jun |
| Abstract | Not available |
| DOI | 10.1109/DAC.1997.597227 |
