- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Perturb And Simplify: Multi-level Boolean Network Optimizer
| Title | Perturb And Simplify: Multi-level Boolean Network Optimizer |
| Publication Type | Conference Paper |
| Year of Publication | 1994 |
| Authors | Chang, S-C, Marek-Sadowska, M |
| Conference Name | Computer-Aided Design, 1994., IEEE/ACM International Conference on |
| Date Published | nov |
| Abstract | Not available |
| DOI | 10.1109/ICCAD.1994.629734 |
