- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Theory of wire addition and removal in combinational Boolean networks
| Title | Theory of wire addition and removal in combinational Boolean networks |
| Publication Type | Journal Article |
| Year of Publication | 2007 |
| Authors | Chang, C-W, Marek-Sadowska, M |
| Journal | Microelectron. Eng. |
| Volume | 84 |
| Pagination | 229–243 |
| ISSN | 0167-9317 |
| DOI | 10.1016/j.mee.2006.02.017 |
