- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
FAR: fixed-points addition & relaxation based placement
| Title | FAR: fixed-points addition & relaxation based placement | 
| Publication Type | Conference Paper | 
| Year of Publication | 2002 | 
| Authors | Hu, B, Marek-Sadowska, M | 
| Conference Name | ISPD '02: Proceedings of the 2002 international symposium on Physical design | 
| Publisher | ACM | 
| Conference Location | New York, NY, USA | 
| ISBN Number | 1-58113-460-6 | 
| DOI | 10.1145/505388.505426 | 
 
        