| Title | Timing-Aware Power-Noise Reduction in Placement |
| Publication Type | Journal Article |
| Year of Publication | 2007 |
| Authors | Yeh, C-Y, Merek-Sadowska, M |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 26 |
| Pagination | 527 -541 |
| Date Published | march |
| ISSN | 0278-0070 |
| Keywords | circuit timing, decoupling capacitance insertion, gate sizing, heuristic algorithm, integrated circuit noise, interference suppression, IR drop, noise estimation, power grid noise, power grids, power integrated circuits, power noise reduction, power timing, sequence of linear programs, standard cell placement tool, switching frequency, timing aware, timing circuits |
| DOI | 10.1109/TCAD.2006.883917 |
