Interconnect resource-aware placement for hierarchical FPGAs

TitleInterconnect resource-aware placement for hierarchical FPGAs
Publication TypeConference Paper
Year of Publication2001
AuthorsSingh, A, Parthasarathy, G, Marek-Sadowska, M
Conference NameComputer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Keywordsarchitecture resources, array size, circuit layout CAD, circuit placement algorithm, clustering, delays, design complexity, empirical measure, field programmable gate arrays, hierarchical FPGAs, integrated circuit interconnections, integrated circuit layout, interconnect resource-aware placement, logic CAD, logic gates, network routing, overall device area, Rent's rule
AbstractUtilizes Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool