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# OBDD minimization based on two-level representation of Boolean functions

Title | OBDD minimization based on two-level representation of Boolean functions |

Publication Type | Journal Article |

Year of Publication | 2000 |

Authors | Wu, Y-L, Fan, H, Marek-Sadowska, M, Wong, CK |

Journal | Computers, IEEE Transactions on |

Volume | 49 |

Pagination | 1371 -1379 |

Date Published | dec |

ISSN | 0018-9340 |

Keywords | binary decision diagrams, Boolean function classes, Boolean functions, evaluation machine, low complexity, minimisation of switching nets, OBDD minimization, series-parallel functions, thin Boolean functions, two-level representation |

Abstract | In this paper, we analyze the basic properties of some Boolean function classes and propose a low complexity OBDD variable ordering algorithm, which is exact (optimum) to some classes of functions and very effective to general two-level form functions. We show that the class of series-parallel functions, which can be expressed by a factored form where each variable appears exactly once, can yield exact OBDD variable orderings in polynomial time. We also study the thin Boolean functions whose corresponding OBDDs can be represented by the form of thin OBDDs in which the number of nonterminal nodes is equal to the number of input variables. We show,that a thin Boolean function always has an essential prime cube cover and the class of series-parallel functions is a proper subset of thin Boolean functions. We propose a heuristic viewing OBDDs as evaluation machines with function cube covers as their inputs and apply a queuing principle in the algorithm design. Our heuristic, the augmented Dynamic Shortest Cube First algorithm, is proven to be optimum for the series-parallel functions and also be very effective for general two-level form functions. Experimental results on a large number of two-level form benchmark circuits show that the algorithm yields an OBDD total size reduction of over 51 percent with only 7 percent CPU time compared to the well-known network-based Fan-in Heuristic implemented in the SIS package. Comparing to the known exact results, ours is only 49 percent larger in size while only uses 0.001 percent CPU time |

DOI | 10.1109/12.895868 |