Modeling crosstalk in resistive VLSI interconnections

TitleModeling crosstalk in resistive VLSI interconnections
Publication TypeConference Paper
Year of Publication1999
AuthorsVittal, A, Chen, LH, Marek-Sadowska, M, Wang, K-P, Yang, S
Conference NameVLSI Design, 1999. Proceedings. Twelfth International Conference On
Date Publishedjan
Keywordscapacitively coupled lines, circuit techniques, crosstalk, crosstalk amplitude, crosstalk modeling, integrated circuit interconnections, integrated circuit layout, integrated circuit modelling, layout techniques, pulse width, resistive VLSI interconnections, transistor sizing, VLSI, wire ordering, wire width optimization
AbstractWe address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk