Wave steering in YADDs: a novel non-iterative synthesis and layout technique

TitleWave steering in YADDs: a novel non-iterative synthesis and layout technique
Publication TypeConference Paper
Year of Publication1999
AuthorsMukherjee, A, Sudhakar, R, Marek-Sadowska, M, Long, SI
Conference NameDesign Automation Conference, 1999. Proceedings. 36th
Keywords0.5 mum, abutment, binary decision diagrams, circuit clocking frequency, CMOS logic circuits, delay equalization, delay estimation, integrated circuit layout, linearized pseudo-symmetric binary decision diagram, logic CAD, logic simulation, low granularity pipelining, network routing, noniterative layout technique, noniterative synthesis technique, physical layout, pipeline processing, routing, simulation results, VLSI realization, wave steering, YADDs, yet another decision diagram
AbstractIn this paper we present a new synthesis and layout approach that avoids the normal iterations between synthesis, technology mapping and layout, and increases routing by abutment. It produces shorter and more predictable delays, and sometimes even layouts with reduced areas. This scheme equalizes delays along different paths, which makes low granularity pipelining a reality, and hence we can clock these circuits at much higher frequencies, compared to what is possible in a conventionally designed circuit. Since any circuit can be clocked at a fixed rate, this method does not require timing-driven synthesis. We propose the logic and layout synthesis schemes and algorithms, discuss the physical layout part of the process, and support our methodology with simulation results