Partitioning sequential circuits on dynamically reconfigurable FPGAs

TitlePartitioning sequential circuits on dynamically reconfigurable FPGAs
Publication TypeJournal Article
Year of Publication1999
AuthorsChang, D, Marek-Sadowska, M
JournalComputers, IEEE Transactions on
Pagination565 -578
Date Publishedjun
Keywordscircuit layout CAD, dynamically reconfigurable FPGAs, field programmable gate arrays, force directed scheduling, gate-level model, logic testing, sequential benchmark circuits, sequential circuits, sequential circuits partitioning, time-multiplexed computation
AbstractA fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus, for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISCAS'89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5 percent with only a 1.1 percent increase in the gate cost compared to traditional FDS