| Title | Wave pipelining YADDs-a feasibility study |
| Publication Type | Conference Paper |
| Year of Publication | 1999 |
| Authors | Mukherjee, A, Marek-Sadowska, M, Long, SI |
| Conference Name | Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 |
| Keywords | 0.5 micron, 715 MHz, binary decision diagrams, circuit CAD, circuit structures, clocking, CMOS digital integrated circuits, CMOS technology, delays, direct mapping, high-speed integrated circuits, integrated circuit layout, layout, logic CAD, pass transistor logic, pipeline processing, PTL, VLSI, wave pipelining, YADD structures, Yet Another Decision Diagrams |
| Abstract | In this paper we study circuit structures obtained from direct mapping to pass transistor logic (PTL) of Yet Another Decision Diagrams (YADDs). These structures have almost equal delays along all the paths which makes wave pipelining possible. We discuss the details of a complete design, clocking and layout. In 0.5 mu;m CMOS technology, YADDs can be clocked at a fixed rate of 715 MHz for any function. Our experimental results suggest that 4 times increase of speed over standard cell design is on the average possible for the price of similar area increase |
| DOI | 10.1109/CICC.1999.777343 |
