| Title | Crosstalk in VLSI interconnections |
| Publication Type | Journal Article |
| Year of Publication | 1999 |
| Authors | Vittal, A, Chen, LH, Marek-Sadowska, M, Wang, K-P, Yang, S |
| Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
| Volume | 18 |
| Pagination | 1817 -1824 |
| Date Published | dec |
| ISSN | 0278-0070 |
| Keywords | circuit optimisation, circuit techniques, crosstalk, crosstalk amplitude, crosstalk computation, crosstalk pulse width, crosstalk reduction, equivalent circuits, integrated circuit interconnections, integrated circuit layout, integrated circuit modelling, integrated circuit noise, layout techniques, resistive capacitively coupled lines, timing, transistor sizing, VLSI, VLSI interconnections, wire ordering, wire width optimization |
| Abstract | We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk |
| DOI | 10.1109/43.811330 |
